There is known a CPU including a function of shifting to a power saving state when in a low load condition so as to reduce power consumption. An example of a technique concerning such a CPU is disclosed in PTL 1 (refer to paragraphs [0002] to [0012]). In the technique disclosed in PTL 1, a power-saving control self-diagnostic device stores the number of times of transition to a power saving state as a flag and determines that the operation rate of the CPU is high when the flag is 0, which indicates that the transition to the power saving state has never been performed. When it is determined so, an alarm is issued so as to detect a state where the operation rate of the CPU is high.